Awesome interview, super interesting to hear from someone who knows the hardware at such a deep level. I'm also really glad that I was able to understand most of it, in no small part because of the course!
That being said, I believe there was a typo when discussing ARM being "weekly" ordered, it should be "weakly" I think.
Super interesting interview. Gosh, would love to see a 2 hour video interview with those questions, and where one would maybe also dig into the older pipeline diagrams, explain some of the hardware details etc.
Great interview. It feels rare to see this kind of interview from the real designers and technical people at these companies, but AMD seems to have taken some strides lately to at least communicate more. The GPU people are more open, working with Tiny Corp on the AI stuff and communicating on Twitter as well.
I worked at AMD as a software performance engineer (for about ten months before going back to my previous company). I worked on all kinds of things from graphics software, to finite element simulations, to large scale computing .In jut that short time I learned at lot about the Zen platform and various ways of doing specific very-low-level optimizations. Good experience. Good interview, thanks for posting.
Some of the stuff in the lab was superb, and unfortunately not all made into actual products. The scalability of the CCD & CCX manufacturing process though, is what impressed me the most.
Hearing about the CPU having the ability to combine consecutive 16k memory into a single TLB entry, it might be another reason for the fault-ahead observed way back in the "Probing OS Page Fault Behavior" video? It would allow the OS to map those pages consecutively.
Not sure if that's actually true or even relevant, but it's nice to see how small drops of information can reveal new angles on past questions.
Great interview, thanks a lot for that! I’m glad you asked what hardware folks would like software engineers could do more of or better. It works both ways, and opening that communication channel could make programs better in the long run
Very interesting interview; I did not get everything but the Performance-Aware course definitely makes it digestible. It is really nice to see that you got some answers to many of the questions that were raised throughout the course.
This is a common misconception, presumably because of the way the cache line sizes are reported on the command line. The per-core.caches on M-series - which is only L1, since L2 is shared - are 64 bytes, not 128.
The 128 byte cache lines are only in the shared L2 cache. So it really is the case that there are no laptop/desktop CPUs right now on wide circulation that don't use 64 byte lines!
Awesome interview, super interesting to hear from someone who knows the hardware at such a deep level. I'm also really glad that I was able to understand most of it, in no small part because of the course!
That being said, I believe there was a typo when discussing ARM being "weekly" ordered, it should be "weakly" I think.
Thank you! Should be corrected now.
- Casey
Fantastic interview, congratulations! I was devouring the transcript like the best novel, I learned a lot from it.
Great interview, would love to hear more from Mike in future :-)
Super interesting interview. Gosh, would love to see a 2 hour video interview with those questions, and where one would maybe also dig into the older pipeline diagrams, explain some of the hardware details etc.
Great interview. It feels rare to see this kind of interview from the real designers and technical people at these companies, but AMD seems to have taken some strides lately to at least communicate more. The GPU people are more open, working with Tiny Corp on the AI stuff and communicating on Twitter as well.
Wow such a fantastic interview! So cool to read this and understand the jargon and what you were talking about! Thanks!
I worked at AMD as a software performance engineer (for about ten months before going back to my previous company). I worked on all kinds of things from graphics software, to finite element simulations, to large scale computing .In jut that short time I learned at lot about the Zen platform and various ways of doing specific very-low-level optimizations. Good experience. Good interview, thanks for posting.
Some of the stuff in the lab was superb, and unfortunately not all made into actual products. The scalability of the CCD & CCX manufacturing process though, is what impressed me the most.
Hearing about the CPU having the ability to combine consecutive 16k memory into a single TLB entry, it might be another reason for the fault-ahead observed way back in the "Probing OS Page Fault Behavior" video? It would allow the OS to map those pages consecutively.
Not sure if that's actually true or even relevant, but it's nice to see how small drops of information can reveal new angles on past questions.
Great interview, thanks a lot for that! I’m glad you asked what hardware folks would like software engineers could do more of or better. It works both ways, and opening that communication channel could make programs better in the long run
Very interesting interview; I did not get everything but the Performance-Aware course definitely makes it digestible. It is really nice to see that you got some answers to many of the questions that were raised throughout the course.
What a great interview!
I wonder how hardware would have evolved differently if it was not for software restricting it.
Really awesome Casey, thanks! A minor note regarding the settling on 64: Apple's M2 is using a 128B cache line.
This is a common misconception, presumably because of the way the cache line sizes are reported on the command line. The per-core.caches on M-series - which is only L1, since L2 is shared - are 64 bytes, not 128.
The 128 byte cache lines are only in the shared L2 cache. So it really is the case that there are no laptop/desktop CPUs right now on wide circulation that don't use 64 byte lines!
- Casey
Thanks for that correction! I'll try to be more careful, didn't consider you could have different sizes.
Great questions, Casey! Wish you had more time.