In each Q&A video, I answer questions from the comments on the previous Q&A video, which can be from any part of the course.
Questions addressed in this video:
[00:03] “After thinking about virtual address space, I had an idea for memory management at the os/cpu level: since only 48 or 57 of the 64 bits in an address are used, we always have the top bit free. What if we make the OS (or the MMU of the CPU) so that if the top bit of a memory address that we read from is 0, we fill the register with 0. This would basically mean that a null pointer would no longer crash your program, and you can read as many bytes as you'd like (2^63), so you can always read a full 0-initalised struct.
This way you only really have to check for 0 if it's a genuine failure case.
I might even go as far as to suggest that the CPU just silently ignores writes to such addresses.
What do you think of this idea? I could see it either work really well or just not at all.”
[03:19] “I've read somewhere that you would like division by 0 to return 0 (me too), and actually, you're in good company: Donald Knuth wrote something similar in Concrete Mathematics when talking about the Iverson Bracket (p24,25) in relation to summations.”
[06:00] “In ‘The Case of the Missing Increment’ you talk about The Ultimate Sadness. I can recall many of my own confrontations with these tasks and feelings over the years, but I've never had a name to give the beast. It truly is The Ultimate Sadness.
Can you please talk more about it — maybe how you've encountered it in the past and what you do to keep your momentum/spirit up while you're working through it?”
[09:37] “Can you publish the listings for the videos Waste and Python Revisited? For example, I'd like to get the RDTSC from Python, which you say you do (but don't show).”
[11:36] “Looking through the AMD die shots on the latest post made me realize I am still not fully sure how exactly an instruction stream gets processed from start to finish, so I went to wikichips for my particular model the 3600 and I learned from Zen onwards there have been 19 pipeline stages which is more than the conceptual stages we've established in the series/what uiCA gives you, I could get my hands on some older AMD64 and Intel pipeline stage diagrams but nothing about the recent models, I'm hoping I just didn't search thoroughly enough and that you'd know where to find this information?
Could you also give some thoughts on why deep pipelining stopped being prioritized, and even regressed back to pipelines under 20 stages?”
[17:25] “I've seen various programmers mentioning about programmer productivity. How would you define being productive? Can you provide a way to quantify this? And are there any things you'd recommend whether that's tools, resources or thought processes to be productive in the programming sense?”
[21:39] “Is part 4 of the course going to delve into things like Multithreading? I have always struggled with it and just couldn't come up with solutions involving it. Usually, I can imagine how my code works, but with Multithreading I just couldn't imagine how the stuff is going to work.”
[22:39] “You've said a few times now that CPUs aren't really designed for well thought-out, optimized code. What do you think a CPU would do differently if it was designed for good software? You gave an example of instruction level parallelism as being important for bad code, but isn't it pretty important for good code too?”
[25:37] “Is there any merit to discussing AMD GPUs or is Nvidia so dominant that AMD isn’t currently worth discussing? As a developer, is there significant overlap between the two? Not trying to start a war.”
[29:38] “A last resort to the Intel communication might be to do what also works with getting attention from politicians: Encourage all listeners to make friendly contact to Intel, requesting <unified simple description of the request>.”
